Notes from Mangaging Project with GNU Make

Cited from the book "Managing Projects with GNU Make"

"The target is the file or thing that must be made. The prerequisites or dependants are those files that must exist before the target can be successfully created. And the commands are those shell commands that will exist before the target can be successfucreate the target from the prerequisites."

"When make is asked to evaluate a rule, it begins by finding the files indicated by the prerequisites and target. If any of the prerequisites has an associated rule, make attempts to update those first. Next, the target file is considered. If any prerequisite is newer than the target, the target is remade by executing the commands."

" To update a line: different target (or to update more than one target) include the target name with make. such as make target"

" --just-print (or -n) tells make to display the commands it would execute for a particular target without actually executing them."

" To set almost any makefile variable on the command line to override the default value or the value set in the makefile. For example:
make mytarget FOO=BAR"

"If no prerequisites are listed to the right, then only the target(s) that do not exist are updated."

"Each command must begin with a tab character. This (obscure) syntax tells make that the characters that follow the tab are to be passed to a subshell for execution. If you accidentally insert a tab as the first character of a noncommand line, make will interpret the following text as a command under most circumstances."

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Explicit Rules:

"Pattern rules use wildcards instead of explicit filenames. get file matching the pattern needs to updated. Implicit rule."

"Implicit rules are either pattern rules or suffix built-in database of rules makes writing makefile."

"A variable is either a dollar sign followed by a single character or a dollar sign followed by a word in."

Wildcards:

"Make's wildcards are identical to the Bourne shell's: ~, *, ?, [...], and [^...]."

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the automatic variable $?: the set of prerequisites that are newer than the target.

$@: the name of the current target.

"You can look at make's default set of rules (and variables) by running make --print-data-base."

"The percent character can be placed anywhere within the pattern but can occur only once."